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[Other resource] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27946 | Author: 王郁 | Hits:

[Embeded-SCM Develop] DDRinterface

Description: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例
Platform: | Size: 25327 | Author: shicheng342 | Hits:

[Other resource] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器
Platform: | Size: 474402 | Author: 张宁 | Hits:

[Other] FPGADDR

Description: 基于FPGA的DDR接口驱动上电初始化的部分已经完成 主要的功能部分尚未编写
Platform: | Size: 7770 | Author: sunshine | Hits:

[Other resource] rtl

Description: DDR控制器 已通过FPGA 验证 大家不要错过哦
Platform: | Size: 52506 | Author: kin | Hits:

[Other resource] ddr_reader

Description: xilinx fpga 的 micoblaze 下的 ddr ram 读程序
Platform: | Size: 1966 | Author: zeng | Hits:

[SCM] upload_code

Description: 每个代码见压缩包内文件名，分别为使用单片机控制AD9627的代码，已在硬件电路实现；基于FPGA的DDR SDRAM控制源代码，将文件夹内文件加入同一工程即可；以及三份FPGA内部学习资料。 C代码开发环境为KeilC，verilog代码开发环境为Quartus。 -See each code within the compressed package file name, respectively, for the use of the AD9627 single-chip control of code, has been in the hardware circuit FPGA-based DDR SDRAM control source code, will be adding a document folder to the same project and three FPGA internal learning materials. C code development environment for KeilC, verilog code development environment for the Quartus.
Platform: | Size: 1746944 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] mictor20110113

Description: ddr控制参考代码,串口通信可以基于此进行二次开发,fpga参考设计，对ddr设计开发有一定的帮助-ddr controller ref code
Platform: | Size: 986112 | Author: wangqijun | Hits:

[VHDL-FPGA-Verilog] DDR_FLASH_VHDL_Verilog

Description: FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
Platform: | Size: 17408 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] DMA_Engine

Description: fpga ddr开发经典必备书籍，是每个fpga开发人员必须具有的-fpga ddr development of classic essential books, is that each developer must have fpga
Platform: | Size: 871424 | Author: 孙乾 | Hits:

[VHDL-FPGA-Verilog] MyDDR

Description: 分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
Platform: | Size: 9427968 | Author: DMANO | Hits:

[VHDL-FPGA-Verilog] ug230.pdf

Description: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration • Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
Platform: | Size: 5851136 | Author: Akalu Lentiro | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: verilog HDL语言实现在FPGA上控制DDR的逻辑，方法简单易懂，适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] ddr_kongzhiqi

Description: fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_

Description: 基于FPGA 的DDR SDRAM 的重要资料 内附代码-FPGA-based DDR SDRAM code containing important information
Platform: | Size: 481280 | Author: 毕禹昕 | Hits:

[Other Embeded program] TimeOutCounter

Description: 用于FPGA内部计数辅助DDR操作，便于开发-TimeOut Counter
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DDRController

Description: DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
Platform: | Size: 7168 | Author: wang | Hits:

[Software Engineering] audio

Description: 一个关于音频播放的fpga驱动代码。流程是从sd卡中读取音频文件，然后缓存到DDR中，再通过一定的时序关系让音频WM8731芯片播放-An audio playback on fpga driver code. The process is to read audio files from sd card and then cached to DDR, and then through a certain timing relationships allow playback of audio WM8731 chip
Platform: | Size: 215040 | Author: lilianghua | Hits:

[VHDL-FPGA-Verilog] XAPP496---Memory

Description: 基于FPGA的内存设计资料，能给FPGA方便的使用DDR做很好的准备，很好的资源啊！-FPGA-based memory design information, ease of use give FPGA DDR do good preparation, good resource ah!
Platform: | Size: 267264 | Author: 李广 | Hits:

[Picture Viewer] ddrdata_show

Description: fpga里ddr数据按一定规格显示为图像-show the data of dddr as a image using matlab
Platform: | Size: 2048 | Author: 孙涛 | Hits:
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